As the feature sizes in modern CMOS processes continue to shrink, the complexity of patterning features (e.g., using 193-nm light sources or EUV light sources) greatly increases. This can result in a prohibitively high cost for mask sets and thus make the small-batch manufacturing of application specific integrated circuits (ASICs) not cost competitive. Electron beam lithography is a straightforward approach to produce feature sizes that scale to the end of the International Technology Roadmap for Semiconductors. However, current electron beam lithography systems have throughput that is too low to be used in production. Existing technologies that that seek to increase the throughput of e-beam lithography tools are complex and can introduce aberrations into the electron beam limiting the ultimate attainable resolution.